Introduction

Transition Metal Dichalcogenides (TMDCs) are non-carbon layered materials and in single layer form they are direct bandgap semiconductors, overcoming graphene’s lack of energy bandgap, vital for optoelectronic applications1,2. Atomically thin TMDCs such as MoS2 offer unique optical, electronic and physical properties such as quantum size effects3,4, mobilities exceeding theoretical values of 410 cm2 V−1 s−15,6, on/off ratios of up to 1010 7,8,9, subthreshold slopes down to 74 mV/dec4,10, beyond the thermal transport limit switching performance9,11 and mechanical flexibility. Altogether this indicates such material’s high potential for replacing and exceeding current material technologies. Weak van der Waals forces between each atomic layer led to “exfoliation and transfer” being one of the first methods used to obtain monolayer TMDCs7,10,3 showing the peak separation and the FWHM of E2g and A1g peaks for a 1 × 1.2 cm2 area.

Fig. 1: MoO3 Ellipsometry results on SiO2/Si.
figure 1

a 6-inch wafer thickness map**. b Real and imaginary part of the refractive index of MoO3. c Real and imaginary part of the refractive index of MoS2.

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The refractive index and extinction coefficients of MoO3 are n = 1.96 and k = 0.08 and that of the resulting MoS2 film n = 5.17 and k = 1.27 at 633 nm. The optical properties of both materials are typical37,38 and are used as a confirmation for wafer-to-wafer reproducibility. After 15 cycles of MoO3 ALD, the thickness of the MoO3 layer as fitted by ellipsometry is 1.31 ± 0.13 nm resulting in 0.87 Å/cycle growth rate.

Monitoring the stoichiometry of MoO3 is important to examine the oxidation level ratios, account for ALD process drifts and adjust for the sulfurisation process, all key when upscaling a process to a fabrication line8. Our contact resistance is defined by the injection barrier height for electrons from the work function of the selected contact metals, but also by the Van der Waals gaps between the MoS2 interlayers and the contact metal layer. We expect that an edge-contact device and a contact metal work function modification can lead to significant improvement in device performance.

Fig. 7: Electrical measurements results of the flexible MoS2 FETs.
figure 7

a Transfer and b output characteristics of a typical FET with channel length of 5 µm and width of 20 µm. c Contact resistance calculated from the on-state resistance of the FETs with different channel lengths. Histograms showing distribution of device d on/off ratio, e field-effect mobility, and f subthreshold slopes (SS) of several measured devices over a 5 × 5 mm2 area.

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To characterise the performance distribution of the fabricated FETs we performed Id-Vg measurements on a range of single FET transistors over a 5 × 5 mm2 area. The measurements revealed an average on/off ratio of 107 (Fig. 7d) while operating between −1 V to +5 V. The field-effect mobility of the devices, was calculated using the equation, \({{{\mathrm{\mu }}}} = \frac{1}{{C_g}}\frac{L}{W}(\frac{{dI_{ds}}}{{dV_{bg}}})\frac{1}{{V_{ds}}}\) where L is the channel length, W is the channel width, (dlds /dVbg) is the slope of transfer characteristic of the devices with drain-to-source voltage Vds = 100 mV, and Cg is the gate capacitance calculated for 30 nm Al2O3 as the gate dielectric. The value of (dlds/dVbg) is estimated by fitting the linear regime of the transfer characteristic curves of MoS2 FETs. The results show that the mobility value of non-passivated devices is up to 32 cm2/Vs while that of passivated devices with P(VDF-TrFE) is up to 55 cm2/Vs (Fig. 7e). The Gaussian distribution of mobilities measured from 15 devices shows a peak around 10 cm2/Vs for non-passivated devices, while for the passivated devices, the mobility distribution peaks at 40 cm2/Vs, indicating a significant improvement in mobility values and variability ought to device passivation. The increased mobility is consistent with the observation of the quenching of the normal to the film homopolar phonon mode which is a characteristic of dual gate and passivated devices70,71 at room temperature, but also more importantly due to the screening of the charge impurities and traps achieved by the passivating fluoropolymer layer72,73. An additional advantage of the encapsulation is that it reduces the exposure of MoS2 to the moisture of the environment and the consequent chemisorption of oxygen; as a result, the TFTs demonstrate a reduced hysteresis74,75. The high field effect mobility of the fabricated FETs presented here is on par with the best of CVD grown MoS2 devices76,77,78,79. The subthreshold slope (SS) values measured from multiple devices also present a Gaussian distribution with a peak at 180 mV/dec (Fig. 7f), with best devices showing SS values down to 80 mV/dec, equivalent to the best reported results for non-negative capacitance FETs of 74 mV/dec10,69. The use of a bilayer MoS2 film is a key element in achieving this performance due to inherent advantages over monolayer films such as the smaller bandgap80, higher mobility81, higher on state current82, lower contact Schottky barrier height83. Supplementary Table 1 and Supplementary Table 2 offer a comparison of growth parameters and electrical performance of similar and pure ALD methods.

Our second electronic device is a FeFET by using a ferroelectric P(VDF-TrFE) layer on top of our MoS2 layer. In these MoS2/P(VDF-TrFE) FeFET devices, when the polarization direction points toward the MoS2 channel, electrons accumulate at the interface between the MoS2 and the P(VDF-TrFE) layer. This downward polarization, thus, results in increased conductivity in the MoS2 channel, representing the device on state. Conversely, when the polarization direction points away from the semiconductor channel, a depletion of electrons occurs at the interface resulting in the decrease in drain-source current, leading to a device off state. A proper screening of the ferroelectric polarization charges can lead to non-volatile retention of the device conductance states over extended periods of time. This feature constitutes FeFETs as one-transistor non-volatile memories that have the potential to increase density in array-level integration.

The FeFETs fabricated in this work show an on/off current ratio of 107, memory window (MW) of 3 V at an operation voltage range of ±5 V (Fig. 8a), 4–5 pA level of gate leakage current in the on state and multiple programmable states in response to single gate pulse writing. Our MoS2 FeFETs outperform earlier flexible memory transistors with organic semiconductors as the channel material. The much lower voltage of operation of our devices is mainly attributed to the thinner 30 nm P(VDF-TrFE) layer compared to typical 100 nm ferroelectric layers used in previous reports36. The key performance matrices presented in ref. 84 place our devices among the most efficient memory transistors reported on flexible substrates. Furthermore, ultrafast switching can be expected from these devices, based upon successful nanosecond pulsed switching demonstrated in our previous work using P(VDF-TrFE)85,86. Devices evaluated at scaled nodes will reveal further performance merits for their integration in memory and in-memory computing arrays.

Fig. 8: Electrical measurements results of the flexible MoS2 FeFETs.
figure 8

a Transfer characteristics of a typical FeFET with channel length of 2 µm and width of 5 µm, demonstrating a memory window of 3 V. b Retention characteristics of the programmed states measured after programming with +5 V or −3 V once followed by repeated reading cycles at 0.5 V. c Repeatability of programming of the FeFETs to multiple conductance states in response to gradually increasing magnitude of gate voltage pulses of millisecond duration. d Distribution of the memory window (MW), e Ion and f Ioff of 14 measured devices from the 5 × 5 mm2 area.

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The FeFETs demonstrate stable, non-volatile data retention (Fig. 8b), when device conductance states are programmed once and read many times with 0.5 V read bias. Further reproducibility of different programmed states was tested with gradually increasing pulse amplitudes of the gate voltage. The drain current (Id) as a function of pulsed gate voltage (Vg) is shown in the top and bottom panels of Fig. 8c, respectively. The results demonstrate that multiple intermediate conductance states, arising from the mixed polarization phase of the FE, can be achieved in our MoS2 FeFETs with high repeatability. Devices were measured over thousands of cycles to multiple conductance states (although few hundred cycles are shown here for clarity) without any significant sign of degradation and breakdown, showing their high endurance to the bias stress. These features make these MoS2 FeFETs suitable, not only for non-volatile data retention, but also as electronic synaptic transistors where post-synaptic currents can be modified in a controllable analog manner, enabling their application in pseudo-crossbar based analog accelerators.

For confirming the homogeneity of device performance over large area, we plotted histograms of FeFET off current (Fig. 8d), on current (Fig. 8e) and MW (Fig. 8f) over 5 × 5 mm2 area. The majority of the devices have similar performance with very few deviations. The off current distribution shows a Gaussian distribution with a peak at around 200 pA while that for the on current shows a peak at around 15 µA. The memory window distribution peaks at around 3.5 V when the FeFET gate voltage is swept in the −5 V to +5 V range. Like the FETs the FeFETs show excellent performance uniformity, demonstrating the potential for large functional device arrays.

The FETs and FeFETs shown here demonstrate high performance properties comparable or exceeding current technology published in literature for comparable devices, highlighting our MoS2 layer’s superior electronic device compatibility but also the performance advantage of an optimised ferroelectric layer. The uniformity of these devices also demonstrates the scalability of this high-performing material for commercial electronic applications.

In this work we have demonstrated the large area uniform growth of 2D TMDCs by a novel ALD process. Highly crystalline MoS2 films were grown on Si/SiO2 substrates using our scalable 2-step process. The first step, growing MoO3 via ALD, results in a film uniformity of 6% over a 6-inch wafer, with a 0.87 Å/cycle growth rate. This stable self-terminated MoO3 growth rate provides a decoupled, accurate and repeatable monitoring and control method for tuning the resulting MoS2 films’ layer number down to a monolayer as verified by Raman, AFM and TEM. The second step, an anneal in H2S is used to control the stoichiometry of the layer at the conversion temperature while the crystallinity is defined at the higher crystallisation temperature of the anneal process. The optimised stoichiometry, imperative for upscaling, has been demonstrated via XPS, resulting in a molybdenum to sulfur atomic ratio of 2.1. AFM and TEM characterisation, highlights the MoS2 films’ low roughness of 146 pm and its continuous nature, with 35 nm sized distinct crystal areas. Thus, this process is ideal for upscaling as it produces smooth continuous layers for subsequent fabrication steps and low device-to-device variation from smaller crystal sizes, without a need for accurate device placement as seen for larger crystals. MoS2 was successfully transferred onto flexible substrates using a chemical free transfer process resulting in two types of electronic devices, FETs and FeFETs. MoS2 FETs over a 5 × 5 mm2 produced an on/off ratio of 107, with best devices exhibiting a SS of down to 80 mV/dec. The MoS2 FeFETs showed a current ratio of 107, alongside a 3 V memory window with an ideal low operation voltage of 5 V, outperforming other flexible FeFETs, by utilising a thin P(VDF-TrFE) layer. Mixed polarisation has been demonstrated, enabling switching between different states to be performed over thousand times with no degradation, highlighting the MoS2 films’ ability to endure high levels of bias stress.

Methods

The substrates used are 6-inch p-type silicon wafers. As a first step 285 nm of thermal SiO2 is grown at 1000 oC in a tube furnace. The wafers are then inserted in a UV/O3 reactor for 10 min to improve the chemical termination of the surface oxide. The next step is to grow the MoO3 using a thermal ALD process in the Cambridge Nanotech Savannah S200 system. The process is based on ref. 87 and uses the precursor bis(tert-butylimido)bis(dimethylamido) molybdenum as a molybdenum source and ozone for the oxidation. Fifteen cycles at 250 oC result in a film of 1.31 ± 0.13 nm of MoO3 as shown in Fig. 1, showing high uniformity over the entire 6-inch wafer. This initial step enables us to have high control over the subsequent number of MoS2 layers, further on in the process.

After the growth, the MoO3 layer is converted into MoS2, via annealing in a tube furnace. The tube dimensions require the wafer to be diced into 2.5 × 2.5 cm2 chips. The chips are placed onto a crucible and then inserted in the tube furnace for film sulfurisation as depicted in Fig. 9. The sulfurisation of the film is performed in an H2S/Ar environment and it involves two steps, one at 550 oC which is used to convert the MoO3 into MoS2 and one at 970 oC which is used to crystallise the film. After conversion and crystallisation, the furnace is left to naturally cool down to room temperature. The described process results in the direct growth of a uniform film of MoS2 directly on SiO2. The film can be used directly to process high-quality rigid electronic devices.

Fig. 9: Schematic of the experimental setup for the growth of the 2D film.
figure 9

MoO3 is grown in an ALD chamber while sulfurisation and crystallisation take place in a tube furnace.

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The ellipsometer measurements were performed with a Whoollam M-2000DI spectroscopic ellipsometer at angles of 65, 70 and 75o for five seconds at each angle. XPS was performed using a Thermofisher Theta Probe with an x-ray spot size of 400 μm at 15 keV and no flood gun. Molybdenum and sulfur peaks were measured at 50 eV pass energy with a dwell time of 50 ms and 20 averaged scans with a step size of 20 meV. The pressure during the measurement was at 2.4 × 10–9 mBar. All XPS results were referenced to adventitious carbon at 284.8 eV. AFM was performed with a Park XE7 AFM in non-contact mode on a 1 μm2 area with a 2048 × 2048 pixels resolution at a 200 mHz scan rate. The AFM employs a very sharp tip with a tip radius of 2 nm and real non-contact tap** mode preserving the sharpness of the tip throughout the measurement. It can therefore offer very high lateral resolution down to just a few nanometers. For the TEM inspection we created a lamella using a Zeiss FIB. The cross-section was analysed using a FEI Tecnai F20 TEM at 200 kV acceleration voltage with a Gatan Multiscan CCD Camera. For the top view HAADF-STEM inspection a film was transferred to a holey silicon nitride TEM grid and analysed using a probe corrected Thermo Fisher Titan Themis TEM at 120 kV. Raman spectroscopy was done with a Renishaw Invia system using a 532 nm laser and a ×50 objective.

As the high reaction temperature of bottom up MoS2 film requires growth on a SiO2/Si substrate, a subsequent transfer to polyimide substrate is made for the formation of flexible devices. The polyimide substrate is formed onto a silicon wafer by spin coating and annealing to offer support for the subsequent processing steps. To form electrical contacts for both gate and source/drain, the substrates are coated with the positive tone photoresist AZ 5214E and the patterns are written with a mask-less lithography process, using a Microtech LW 405 laser writer. To form the gate dielectric, 30 nm of alumina is grown on the polyimide using thermal ALD in a Beneq TFS-500, which is subsequently patterned by laser lithography and etched in a 20:1 buffered HF solution.

After the sulfurisation of the films, the chips are spin coated at 3500 rpm for 60 seconds with a 2% polystyrene/Toluene solution (PS molecular weight: 280,000 g/mol) and baked at 90 oC for 10 min88. They are then dipped into a deionised water bath and within a minute the film is lifted off the substrate and floats on the surface. The MoS2 layer is then transferred onto the patterned polyimide and baked at 80 oC for 10 min to remove the bulk of the water and subsequently at 120 oC. The substrates are then left in a toluene bath for 72 h. Upon removal they are rinse in DI water and dried with a nitrogen gun before they are left in ambient cleanroom conditions to dry for a day. This results in a clean MoS2 surface ready to be patterned.

The FET transistors and FeFET devices are fabricated on flexible polyimide substrates that are mechanically supported on Si backplates. For the FET transistors, a patterned back-gate metal layer of 2 nm Ti and 50 nm Au is deposited using e-beam evaporation followed by lift-off. Next, a 30 nm thick Al2O3 layer is grown by ALD at 300 oC. Vias are opened using wet oxide etching followed by oxygen plasma cleaning. Next, the MoS2 layer is transferred, the carrier film is washed, and the channel area is defined using a mask-less laser writer lithography process by a Microtech Laser Writer 405. MoS2 areas outside of the channel are etched using an SF6/O2 plasma. Drain-source contacts are patterned on top of MoS2 using a lithography step and Au (3 nm), Ti (2 nm), and Au (50 nm) electrodes are deposited by e-beam evaporation at room temperature followed by lift-off. The devices are then annealed at 200 °C in a vacuum furnace for 2 h to remove resist residues and to improve the contact resistance. To protect the MoS2 layer from atmospheric adsorbates, we fabricated a batch of devices with a passivation layer of 100 nm thick spin-coated fluoropolymer P(VDF-TrFE) followed by a drying step at 90 °C in a furnace for 2 h. Although this is the same material we use as a ferroelectric layer, P(VDF-TrFE) does not attain its polar β-phase when annealed at 90 °C and therefore remains as a purely amorphous, dielectric layer.

For the FeFET devices, two additional processing steps are implemented on top of the FET devices. A ferroelectric (FE) layer consisting of P(VDF-TrFE) (70:30 mol%) copolymer and a top gate metal are deposited on top of the channel. The FE layer is made from ferroelectric polymer powder (from Piezotech) dissolved in Methyl Ethyl Ketone (MEK) at 0.5 wt% dilution and the solution is spin coated on top of MoS2. First, the spin-coated films are dried at 100 °C for 10 min and then they are annealed in vacuum at 135 °C for 2 h to improve their crystallinity and obtain the ferroelectric β-phase. The FeFETs consist of a 30 nm thick P(VDF-TrFE) gate insulator layer directly between the MoS2 channel and the Au gate metal electrode (30 nm thin Au patterned by lithography and etched using wet etching). The thickness of the ferroelectric films was characterised by profilometry using a Si/SiOx/P(VDF-TrFE)/Au capacitor structure.

The size of the MoS2 channel for both the FETs and the FeFETs varied between ≈ 2 (L) × 5 (W)−20 (L) × 40 (W) µm2.

All measurements were performed using a Keithley 4200A-SCS parameter analyzer in a probe station. Continuous transfer characteristics measurements were performed by applying swee** voltage at the gate terminal under a continuous bias voltage between drain and source contacts. When operating the double gated transistors as FeFETs, the bottom gate contact can either be grounded or can be set at a fixed bias that can modulate the operating point of the transistors. Retention measurements were performed by programming the devices once with +5 V or −3 V pulse followed by repeated reading at 0.5 V. Repeatability of multiple programmed states of the FeFETs were tested using gradually increasing magnitude of gate voltage pulses of millisecond duration over several thousands of cycles. These measurements also provided information on the endurance of the devices in response to repeated bias stress. All measurements were carried out under atmospheric conditions and room temperature without illumination. In the case of the FET transistors, the P(VDF-TrFE) layer on top of MoS2 acts as the encapsulation layer. Devices were stored in a N2 filled glove box between measurements.